>Historyneverlies2: Add P-core L0 cache

2024-06-06T10:35:11Z

Add P-core L0 cache

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{{Infobox
| title = {{{name|<includeonly>{{PAGENAMEBASE}}</includeonly>}}}
| image = {{#invoke:InfoboxImage|InfoboxImage|image={{{image|}}}|size={{{image_size|}}}|sizedefault=frameless|alt={{{alt|}}}}}
| caption = {{{caption|}}}

| label1 = Launching
| data1 = {{{launching|}}}
| label2 = Launched
| data2 = {{{launched|}}}
| label3 = Discontinued
| data3 = {{{discontinued|}}}
| label4 = Designed by
| data4 = {{{designedby|}}}
| label5 = Manufactured by
| data5 = {{unbulleted list
| {{{manuf1|}}}
| {{{manuf2|}}}
| {{{manuf3|}}}
| {{{manuf4|}}}
| {{{manuf5|}}}
}}
| label6 = Fabrication process
| data6 = {{unbulleted list
| {{{process1|}}}
| {{{process2|}}}
| {{{process3|}}}
| {{{process4|}}}
| {{{process5|}}}
| {{{process6|}}}
| {{{process7|}}}
| {{{process8|}}}
| {{{process9|}}}
}}
| label7 = Codename(s)
| data7 = {{unbulleted list
| {{{codename|}}}
| {{{codename1|}}}
| {{{codename2|}}}
| {{{codename3|}}}
| {{{codename4|}}}
| {{{codename5|}}}
}}
| label8 = Platform(s)
| data8 = {{unbulleted list
| {{{platform1|}}}
| {{{platform2|}}}
| {{{platform3|}}}
| {{{platform4|}}}
| {{{platform5|}}}
}}

| header10 = {{ #if: {{{branding|}}}{{{generation|}}}{{{socket1|}}}{{{socket2|}}}{{{socket3|}}}{{{socket4|}}}{{{socket5|}}} | Branding }}
| label11 = Brand name(s)
| data11 = {{{branding|}}}
| label12 = Generation
| data12 = {{{generation|}}}
| label13 = Socket(s)
| data13 = {{unbulleted list
| {{{socket1|}}}
| {{{socket2|}}}
| {{{socket3|}}}
| {{{socket4|}}}
| {{{socket5|}}}
}}

| header14 = {{ #if: {{{instructions-set|}}}{{{instructions|}}}{{{extensions|}}}{{{extensions1|}}}{{{extensions2|}}}{{{extensions3|}}}{{{extensions4|}}}{{{extensions5|}}}{{{core-arch|}}}{{{p-core-arch|}}}{{{e-core-arch|}}} | Instructions & Architecture }}
| label15 = Instructions set
| data15 = {{{instructions-set|}}}
| label16 = Instructions
| data16 = {{{instructions|}}}
| label17 = Extensions
| data17 = {{unbulleted list
| {{{extensions|}}}
| {{{extensions1|}}}
| {{{extensions2|}}}
| {{{extensions3|}}}
| {{{extensions4|}}}
| {{{extensions5|}}}
}}
| label18 = Core architecture
| data18 = {{{core-arch|}}}
| label19 = P-core architecture
| data19 = {{{p-core-arch|}}}
| label20 = E-core architecture
| data20 = {{{e-core-arch|}}}

| header21 = {{ #if: {{{core-codename|}}}{{{ccd-codename|}}}{{{core-count|}}}{{{peak-clock|}}}{{{l1-cache|}}}{{{l2-cache|}}}{{{l3-cache|}}}{{{p-l0-cache|}}}{{{p-l1-cache|}}}{{{p-l2-cache|}}}{{{p-l3-cache|}}}{{{e-l1-cache|}}}{{{e-l2-cache|}}}{{{e-l3-cache|}}} | Cores }}
| label22 = Core codename
| data22 = {{{core-codename|}}}
| label23 = CCD codename
| data23 = {{{ccd-codename|}}}
| label24 = Core count
| data24 = {{#if:{{{core-count|}}}|Up to {{{core-count|}}}}}
| label25 = Peak core clock
| data25 = {{#if:{{{peak-clock|}}}|Up to {{{peak-clock|}}} {{{peakclock-unit|}}} }}
| label26 = L1 cache
| data26 = {{{l1-cache|}}}
| label27 = L2 cache
| data27 = {{{l2-cache|}}}
| label28 = L3 cache
| data28 = {{{l3-cache|}}}

| label29 = P-core L0 cache
| data29 = {{{p-l0-cache|}}}
| label31 = P-core L1 cache
| data31 = {{{p-l1-cache|}}}
| label32 = E-core L1 cache
| data32 = {{{e-l1-cache|}}}
| label33 = P-core L2 cache
| data33 = {{{p-l2-cache|}}}
| label34 = E-core L2 cache
| data34 = {{{e-l2-cache|}}}
| label35 = P-core L3 cache
| data35 = {{{p-l3-cache|}}}
| label36 = E-core L3 cache
| data36 = {{{e-l3-cache|}}}

| header37 = {{#if:{{{graphics-arch|}}}{{{cu-count|}}}{{{eu-count|}}}{{{graphics-clock|}}}{{{gpu-model1|}}}{{{gpu-model2|}}}{{{gpu-model3|}}}{{{gpu-model4|}}}{{{gpu-model5|}}}{{{gpu-model6|}}}{{{gpu-model7|}}}{{{gpu-model8|}}}{{{gpu-model9|}}} | Graphics}}
| label39 = Graphics architecture
| data39 = {{{graphics-arch|}}}
| label40 = Model(s)
| data40 = {{unbulleted list
| {{{gpu-model1|}}}
| {{{gpu-model2|}}}
| {{{gpu-model3|}}}
| {{{gpu-model4|}}}
| {{{gpu-model5|}}}
| {{{gpu-model6|}}}
| {{{gpu-model7|}}}
| {{{gpu-model8|}}}
| {{{gpu-model9|}}}
}}
| label41 = Compute Units
| data41 = {{#if:{{{cu-count|}}}|Up to {{{cu-count|}}} CUs}}
| label42 = Execution Units
| data42 = {{#if:{{{eu-count|}}}|Up to {{{eu-count|}}} EUs}}
| label43 = Xe Cores
| data43 = {{#if:{{{xe-count|}}}|Up to {{{xe-count|}}} Xe Cores}}
| label44 = Peak graphics clock
| data44 = {{#if: {{{graphics-clock|}}}|{{{graphics-clock|}}} {{{graphics-clockunit|}}}}}

| header45 = {{ #if: {{{npu-arch|}}}{{{npu-tops|}}}{{{npu-clock|}}} | NPU }}
| label46 = Architecture
| data46 = {{{npu-arch|}}}
| label47 = TOPS
| data47 = {{{npu-tops|}}}
| label48 = Clock speed
| data48 = {{#if: {{{npu-clock|}}}|{{{npu-clock|}}} {{{npu-clockunit|}}}}}

| header49 = {{ #if: {{{memory-type|}}}{{{memory-channels|}}}{{{amountmemory|}}} | Memory Support }}
| label50 = Type
| data50 = {{{memory-type|}}}
| label51 = Memory channels
| data51 = {{{memory-channels|}}}
| label52 = Maximum capacity
| data52 = {{{amountmemory|}}}

| header53 = {{ #if: {{{pcie-support|}}}{{{pcie-lanes|}}}{{{cxl-support|}}}{{{upi-links|}}}{{{dmi-version|}}}{{{ht-version|}}}{{{ht-speed|}}} | I/O }}
| label54 = PCIe support
| data54 = {{{pcie-support|}}}
| label55 = PCIe lanes
| data55 = {{{pcie-lanes|}}}
| label56 = CXL support
| data56 = {{{cxl-support|}}}
| label57 = UPI links
| data57 = {{{upi-links|}}}
| label58 = DMI version
| data58 = {{{dmi-version|}}}
| label59 = HyperTransport version
| data59 = {{{ht-version|}}}
| label60 = HyperTransport speeds
| data60 = {{{ht-speed|}}}

| header61 = {{ #if: {{{predecessor|}}}{{{variant|}}}{{{successor|}}} | History }}
| label62 = Predecessor
| data62 = {{{predecessor|}}}
| label63 = Variant
| data63 = {{{variant|}}}
| label64 = Successor
| data64 = {{{successor|}}}
}}
<noinclude>{{Documentation}}</noinclude>

Template:Infobox CPU series - Revision history

>Historyneverlies2: Add P-core L0 cache